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dbis
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Publications
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2012
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Sorting Networks on FPGAs
VLDBJ Reviews
other well-known sorting algorithms (sections 6, 7.3, 8.3) ). Two use cases: a streaming median operator (section 7); and a sorting co-processor (section 8). The paper is well written and easily understandable [...] again a reference to the relevant Xilinx data sheet is sufficient. VHDL code for a comparator on page 8 is absolutely trivial and well known. I am not sure if you should show this code in research paper. [...] not clear, however, how such networks can be used in system design. For example, in sections 7 and 8 just simple sorting networks were examined for use cases. Indeed, if N=64 (see page 14), m=32 there …
